1. Technical Field
The present invention relates to a multichip device, including a first terminal and provided with a first circuit chip and a second circuit chip mounted thereon, and particularly relates to a multichip device that is switchable between the first connection status and the second connection status.
2. Related Art
Conventionally, multichip devices having a plurality of circuit chips, which are utilized in combination and are mounted on one device base member, are developed for practical use, and the devices are called as system in package (SIP). Here, a conventional example of such multichip device will be described as follows in reference to FIG. 7.
A multichip device 100 includes a rectangular device base member 110 composed of an insulating substrate or the like. External terminals 111 composed of a plurality of first terminals are formed in a circumference of such device base member 110.
In addition, the device base member 110 is provided with a main chip 120 serving as a first circuit chip and a peripheral chip 130 serving as a second circuit chip mounted thereon. However, the peripheral chip 130 is mounted through an interposer substrate 140.
The main chip 120 is composed of chip components formed as so-called microcomputer, and digital hardware such as a central processing unit (CPU), a read only memory (ROM), a random access memory (RAM), an interface (I/F) unit and the like are included therein (not shown).
The main chip 120 is provided with main terminals 121 serving as a plurality of second terminals formed on the outer surface thereof. Then, an internal CPU or the like is appropriately connected to such main terminals 121. The peripheral chip 130 is also formed as a chip component, and an analog circuit or the like that is capable of supplementing functions of the main chip 120 is contained therein as various functional circuits (not shown).
The peripheral chip 130 is provided with outside terminals 131 serving as a plurality of third terminals and inside terminals 132 serving as a plurality of fourth terminals. Internal functional circuits are appropriately connected to the terminals 131 and 132.
In addition to above, terminals of the peripheral chip 130 connected to external terminals 111 are referred to as outside terminals 131, and terminals thereof connected to the main chip 120 are referred to as inside terminals 132. Nevertheless, these are just temporary names for simplifying the description, and thus there is no special semantic in these names.
The interposer substrate 140 is provided with a plurality of connection terminals 141 formed in the circumference or the surface thereof. The connection terminals 141 are, in turn, connected via printed wirings 142 and 143.
These printed wirings 142 and 143 are composed of the printed wiring 142 of a single-line form that simply relays connections between the main chip 120 and the external terminals 111 and the printed wiring 143 of a two-way form that connections among the main chip 120, the peripheral chip 130 and the external terminals 111.
In the multichip device 100 illustrated here, the main chip 120 is directly mounted on the device base member 110 as described above. On the other hand, the peripheral chip 130 is mounted via the interposer substrate 140.
Many of the main terminals 121 of the main chip 120 are connected to the peripheral external terminals 111 via bonding wires 144. On the other hand, the part of the main terminals 121 are connected to the connection terminals 141 of the circumference of the interposer substrate 140 facing thereof.
The outside terminals 131 of the peripheral chip 130 are connected to the peripheral external terminals 111 via the bonding wires 144. On the other hand, the inside terminals 132 are connected to the connection terminals 141 in the surface of the interposer substrate 140 facing thereof.
Consequently, in such multichip device 100, several of the main terminals 121 of the main chip 120, several of the inside terminals 132 of the peripheral chip 130 and several of the external terminals 111 are mutually connected via the printed wiring 143 of two-way form in the interposer substrate 140.
The multichip device 100 having the structure as described above involves switchable operating modes of, for example, a normal mode that provides a first connection status and a testing mode that provides a second connection status.
In the normal mode, the multichip device 100 is incorporated in electronic equipment such as, for example, a portable telephone, and various types of circuits that are contained in the electronic equipment are connected to the external terminals 111 to serve as external circuits (not shown).
In such case, no external circuit is connected to the external terminals 111 that are connected via the printed wiring 143 of two-way form in the interposer substrate 140. Consequently, mutual communication between the main chip 120 and the peripheral chip 130 without an obstacle can be achieved by the printed wirings 143.
In such circumstance, for example, the main chip 120 and the peripheral chip 130 are in the normal mode with the aid of the electronic equipment. Consequently, the main chip 120 and the peripheral chip 130 are in the condition for conducting the normal operation.
In the case, the external circuits communicate with main chip 120 and peripheral chip 130, and the main chip 120 also mutually communicates with the peripheral chip 130. Consequently, the multichip device 100 functions as a part of the electronic equipment.
In addition to above, manufacturers who manufacture and deliver the multichip device 100 as described above ordinary inspect the multichip device 100, before delivering the multichip device 100. In the inspection, the multichip device 100 is loaded in a testing equipment (not shown), and the testing terminal of a testing equipment is appropriately connected to the external terminal 111.
Under such circumstance, for example, the main chip 120 and the peripheral chip 130 are in the testing mode with the aid of the testing equipment. Consequently, the main chip 120 and the peripheral chip 130 are in the condition for conducting the testing operation.
Such testing operations includes not only a simultaneous testing for the main chip 120 and the peripheral chip 130 under a connection status that is similar to the connection status in the normal operation, but also a testing for only the main chip 120.
In such case, high impedance is put for the inside terminals 132 of the peripheral chip 130. Consequently, communication between the testing equipment and the main chip 120 without an obstacle can be achieved with the aid of the two-way form printed wiring 143 of the interposer substrate 140.
Currently, there are various proposals for the multichip device 100 as described above (see, for example, Japanese Patent Laid-Open NO. 2004-085366). Besides, controlling an I/O port by employing a dedicated circuit is proposed, though such proposal is not related to the multichip device (see, for example, Japanese Patent Laid-Open NO. 2003-296296).
In the multichip device 100 described above, several of the main terminals 121 of the main chip 120 are connected to several of the inside terminals 132 of the peripheral chip 130 via the printed wiring 143 of two-way form in the interposer substrate 140, and are also connected to several of the external terminals 111.
Consequently, communication between the main chip 120 and the peripheral chip 130 can be achieved via the main terminals 121 and inside terminals 132 in the normal mode, and communication of the main chip 120 and the peripheral chip 130 selectively with the external terminals 111 can be achieved in the testing mode.
However, such external terminals 111 are not utilized in the normal mode as described above, and thus are formed for conducting the testing. Similarly, the printed wirings 143 of two-way form interposer substrate 140 is also formed for conducting the testing. In other words, the interposer substrate 140 is required for conducting the testing.
Further, it may be often difficult that some of the main terminals 121 located in the positions opposed to the peripheral chip 130 of the main chip 120 are connected to the external terminals 111 directly, instead of the peripheral chip 130, via the bonding wires 144.
In such case, the printed wirings 142 and 143 of the interposer substrate 140 are also utilized to connect some of the main terminals 121 opposed to the peripheral chip 130 to the external terminals 111.
In other words, the interposer substrate 140 is still required for connecting of the main terminals 121 in the above-described locations with the external terminals 111. Consequently, the dimension of the multichip device 100 is increased due to the presences of the external terminals 111 and the interposer substrate 140, which are not required for the normal operation, and the productivity thereof is reduced.